Existing computing devices typically perform scalar data processing. Scalar processors may operate on only one data object at a time, and thus, are single instruction, single data (SISD) processors. Vectorization is a single instruction, multiple data (SIMD) mode of data processing that may allow an instruction to operate on multiple data objects in parallel in a single processor core. SIMD processing offers advantages over SISD processing, especially in terms of the speed at which data may be processed. A substantial speed advantage may be realized by, for example, grouping data reads to be performed concurrently and doing the same for data writes. In at least one embodiment, the addresses corresponding to locations from which the data will be read, or to which the data will be written, may be consolidated into dynamic arrays or “vectors.” Executing the data transactions in parallel is much faster than performing them serially. As a result, a fixed amount of processing capacity may be able to process a lot more information using vectorization.
While vectorization may be able to achieve substantial increases in processor throughput, the vectorization of general purpose applications may be limited due to dynamic cross-iteration dependencies and complex control flow. Conflicts may occur within a vector, between different vector elements, etc. For example, a conflict may arise in scenarios where in a sequence of instructions data is written to a location one or more times before a read occurs. In this instance, performing all reads and/or writes concurrently may result in a timing issue that causes the wrong data to be read. When potential conflicts in or between vectors occur infrequently, not using vectorization results in underutilization of hardware capacity. To enable the implementation of vectorization, systems are being developed to help determine potential conflicts between vector elements. While conflict detection systems may facilitate vectorization when no conflict is determined, and thus, to realize increased processing speed, any performance gain may be to some degree nullified by the burden imposed by conflict detection. In particular, existing conflict detection systems may provide high detection accuracy, but may slow the system with added data processing overhead.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications and variations thereof will be apparent to those skilled in the art.